Semiconductor structure and formation method thereof

ABSTRACT

A semiconductor structure and a formation method thereof are provided. The formation method includes: providing a base, a dummy gate structure being formed on the base, a source/drain doping region being formed in the base on both sides of the dummy gate structure, a dielectric layer being formed on the base exposed by the dummy gate structure, and the dielectric layer covering the source/drain doping region; etching the dielectric layer on both sides of the dummy gate structure to form a contact hole exposing the source/drain doping region; forming a contact plug in the contact hole, the contact plug being electrically connected to the source/drain doping region; after forming the contact plug, removing the dummy gate structure, and forming a gate opening in the dielectric layer; and forming a gate structure in the gate opening. Embodiments of the present disclosure are advantageous to simplify process complexity and increase process windows.

RELATED APPLICATIONS

The present application is a divisional of U.S. application Ser. No.16/659,932, filed Oct. 22, 2019 (still pending), which claims priorityto Chinese Patent Appln. No. 201910577105.6, filed Jun. 28, 2019, theentirety of each are incorporated by reference.

BACKGROUND Technical Field

Embodiments and implementations of the present disclosure relate to thefield of semiconductor manufacturing, and in particular, to asemiconductor structure and a formation method thereof.

Related Art

As MOSFET devices are scaled down, devices require a high dielectricconstant (high k) as a gate insulating layer and metal as a stackstructure of a gate conductive layer to suppress the problems of highgate leakage and reduced gate capacitance due to polysilicon gatedepletion problems. In order to more effectively control the profile ofa gate stack, a gatelast process is generally used in the industry. Thatis, a dummy gate made of polysilicon or the like is usually deposited ona substrate. After an interlayer dielectric layer (ILD) is deposited,the dummy gate is removed, and then a stack of high-k metal gate (HK/MG)layers is filled in a reserved gate trench. Thereafter, the ILD isetched to form a contact hole exposing a source/drain doping layer, anda metal material is deposited in the contact hole to form a contactplug.

However, as device integration increases, device feature sizes continueto shrink, and gate lengths and source/drain region sizes are scaleddown. When a size of the source/drain doping layer is small, it poses agreat challenge to a contact process. This is mainly reflected in highrequirements for the critical dimensions (CD) and overlay ofphotoetching. For example, in order to reduce the series resistance of acontact itself, it is required that the size of a contact hole issubstantially close to the size of a source/drain region. If the size ofthe contact hole is significantly smaller than the size of thesource/drain region (especially a heavily doped source/drain dopinglayer), this requires a higher critical dimension for photoetching,while the series resistance of the smaller contact plug itself will belarger. In addition, since a distance between the contact hole and agate is reduced, the overlay of contact hole photoetching is required tobe high. If the overlay is large, a short circuit between the contactplug and the gate is caused.

SUMMARY

Embodiments and implementations of the present disclosure are directedto a semiconductor structure and a method for forming a semiconductorstructure, which simplify process complexity and increase processwindows.

To address the aforementioned problems, embodiments and implementationsof the present disclosure provide a method for forming a semiconductorstructure. In one form, a method for forming a semiconductor structureincludes: providing a base, a dummy gate structure being formed on thebase, where a source/drain doping region is formed in the base on bothsides of the dummy gate structure, a dielectric layer is formed on thebase exposed by the dummy gate structure, and the dielectric layercovers the source/drain doping region; etching the dielectric layer onboth sides of the dummy gate structure to form a contact hole exposingthe source/drain doping region; forming a contact plug in the contacthole, the contact plug being electrically connected to the source/draindoping region; after forming the contact plug, removing the dummy gatestructure, and forming a gate opening in the dielectric layer; andforming a gate structure in the gate opening.

The present disclosure also provides a semiconductor structure. In oneform, a semiconductor structure includes: a base; a dummy gatestructure, located on the base; a source/drain doping region, located inthe base on both sides of the dummy gate structure; a dielectric layer,located on the base exposed by the dummy gate structure, the dielectriclayer exposing a top of the dummy gate structure; and a contact plug,located in the dielectric layer on a top of the source/drain dopingregion, where the contact plug is electrically connected to thesource/drain doping region.

Compared with the prior art, technical solutions of embodiments andimplementations of the present disclosure have the following advantages:

In embodiments and implementations of the present disclosure, adielectric layer on both sides of the dummy gate structure is etchedfirst to form a contact hole exposing the top of the source/drain dopingregion in the dielectric layer, and then a contact plug is formed in thecontact hole. After a gate opening is formed by removing the dummy gatestructure subsequently and a gate structure is formed in the gateopening, the steps of removing the gate structure of a partial thicknessand forming a protective layer on the top of the remaining gatestructure are not required additionally, thereby facilitatingsimplification of the process complexity and reduction of the processdifficulty. Moreover, the embodiments of the present disclosureeliminate the step of removing the gate structure of a partialthickness, so that it is unnecessary to form a dummy gate structure anda gate structure having an excessively large height. Accordingly, it isadvantageous to increase the process windows for forming the dummy gatestructure, removing the dummy gate structure and forming the gatestructure. In summary, the embodiments of the present disclosure areadvantageous to simplify the process complexity and increase the processwindows.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-6 are schematic diagrams corresponding to various steps in amethod for forming a semiconductor structure.

FIGS. 7-17 are schematic diagrams corresponding to various steps in oneform of a method for forming a semiconductor structure according to thepresent disclosure.

DETAILED DESCRIPTION

At present, the process steps of forming a gate structure and a contactplug are complicated, and the process windows are small. A method forforming a semiconductor structure is now combined to analyze the reasonsfor the complicated process steps and the small process windows.

Referring to FIGS. 1-6, schematic diagrams corresponding to varioussteps in a method for forming a semiconductor structure are shown.

Referring to FIG. 1, a base 1 is provided, where a dummy gate structure2 is formed on the base 1, a source/drain doping region 3 is formed inthe base 1 on both sides of the dummy gate structure 2, a dielectriclayer 4 is formed on the base 1 exposed by the dummy gate structure 2,and the dielectric layer 4 covers the source/drain doping region 3.

Referring to FIG. 2, the dummy gate structure 2 (as shown in FIG. 1) isremoved, and a gate opening 5 is formed in the dielectric layer 4.

Referring to FIG. 3, a gate structure 6 is formed in the gate opening 5.

Referring to FIG. 4, the gate structure 6 of a partial thickness isetched back to form a groove (not shown) in the dielectric layer 4, anda protective layer 7 filled in the groove is formed.

Specifically, the step of forming the protective layer 7 includes:filling a protective material layer (not shown) in the groove, theprotective material layer also covering the top of the dielectric layer4; and removing the protective material layer above the top of thedielectric layer 4 by using a planarization process, the remainingprotective material layer located in the groove serving as theprotective layer 7.

Referring to FIG. 5, a self-aligned contact (SAC) etching process isused, and the protective layer 7 is used as an etch barrier layer toetch the dielectric layers 4 on both sides of the gate structure 6 toform a contact hole 8 exposing the source/drain doping region 3.

Referring to FIG. 6, a contact plug 9 is formed in the contact hole 8.

In the field of semiconductors, a side wall (not marked) is also formedon a sidewall of the gate structure 6 for protecting the sidewall of thegate structure 6 and for defining a formation region of the source/draindoping region 3. The protective layer 7 and the side wall can functionto define an etch stop position in a self-aligned contact etchingprocess for forming the contact hole 8, and therefore, even if theproblem of overlay shift exists in the process of forming the contacthole 8, the etching process can be prevented from causing loss to thegate structure 6, thereby preventing the contact plug and the gatestructure 5 which are subsequently filled in the contact hole 8 frombeing short-circuited.

However, in the formation method, it is necessary to form the dummy gatestructure 2 and the gate structure 6 higher than a preset processheight, which increases the process difficulty of forming and removingthe dummy gate structure 2 and forming the gate structure 6. Moreover,the gate structure 6 is generally a metal gate structure, the process ofetching back the gate structure 6 of a partial thickness is difficult,the process stability is low, and large side effects are easilygenerated. In addition, in the process of forming the protective layer7, the formation of a protective material layer filled in the grooveeasily causes defects such as voids, and in the step of performing theplanarization process, the removal selection of the protective materiallayer and the dielectric layer 4 is relatively small, it is difficult tocontrol a stop position of the planarization process, and the difficultyof the planarization process is large. In summary, the formation methodhas a complicated process flow, a large process difficulty and a smallprocess window.

To address the technical problem, embodiments and implementations of thepresent disclosure provide a method for forming a semiconductorstructure. One form of a formation method includes: providing a base, adummy gate structure being formed on the base, where a source/draindoping region is formed in the base on both sides of the dummy gatestructure, a dielectric layer is formed on the base exposed by the dummygate structure, and the dielectric layer covers the source/drain dopingregion; etching the dielectric layer on both sides of the dummy gatestructure to form a contact hole exposing the source/drain dopingregion; forming a contact plug in the contact hole, where the contactplug is electrically connected to the source/drain doping region; afterforming the contact plug, removing the dummy gate structure, and forminga gate opening in the dielectric layer; and forming a gate structure inthe gate opening.

In embodiments and implementations of the present disclosure, adielectric layer on both sides of the dummy gate structure is etchedfirst to form a contact hole exposing the top of the source/drain dopingregion in the dielectric layer, and then a contact plug is formed in thecontact hole. Therefore, after a gate opening is formed by subsequentlyremoving the dummy gate structure and forming a gate structure in thegate opening, the steps of removing the gate structure of a partialthickness and forming a protective layer on the top of the remaininggate structure are not required additionally, thereby facilitatingsimplification of the process complexity and reduction of the processdifficulty. Moreover, embodiments and implementations of the presentdisclosure eliminate the step of removing the gate structure of apartial thickness, so that it is unnecessary to form a dummy gatestructure and a gate structure having an excessively large height.Accordingly, it is advantageous to increase the process windows forforming the dummy gate structure, removing the dummy gate structure andforming the gate structure. In summary, embodiments and implementationsof the present disclosure are advantageous to simplify the processcomplexity and increase the process windows.

To make the above objects, features and advantages of embodiments andimplementations of the present disclosure more clearly understood,specific embodiments and implementations of the present disclosure aredescribed in detail below with reference to the accompanying drawings.

FIGS. 7-17 are schematic diagrams corresponding to various steps in oneform of a method for forming a semiconductor structure according to thepresent disclosure.

Referring to FIG. 7, a base 100 is provided, a dummy gate structure 110is formed on the base 100, a source/drain doping region 115 is formed inthe base 100 on both sides of the dummy gate structure 110, a dielectriclayer 116 is formed on the base 100 exposed by the dummy gate structure110, and the dielectric layer 116 covers the source/drain doping region115.

The base 100 is used to provide a process platform for subsequentprocesses.

In some implementations, the base 100 is used to form a planar fieldeffect transistor, and the base 100 accordingly includes only asubstrate (not marked). In other implementations, when the base is usedto form a fin field effect transistor (FinFET), the base accordinglyincludes a substrate and a fin that protrudes from the substrate.

In some implementations, the substrate is a silicon substrate. In otherimplementations, the material of the substrate may also be othermaterials such as germanium, silicon germanide, silicon carbide, galliumarsenide or indium gallide, and the substrate can also be other types ofsubstrates such as a silicon substrate on an insulator or a germaniumsubstrate on an insulator. The material of the substrate may be amaterial suitable for process requirements or easy to integrate.

The dummy gate structure 110 occupies a spatial position for subsequentformation of a gate structure.

In some implementations, the dummy gate structure 110 is a single-layerstructure, the dummy gate structure 110 includes only a dummy gate layer(not marked), and the material of the dummy gate layer is polysilicon.

In other implementations, the dummy gate structure may also be a stackedstructure, the dummy gate structure accordingly includes a dummy gateoxide layer and a dummy gate layer located on the dummy gate oxidelayer, and the material of the dummy gate oxide layer may be siliconoxide or silicon oxynitride.

In some implementations, a gate mask layer 102 is further formed on thetop of the dummy gate structure 110.

The gate mask layer 102 is located on the top of the dummy gatestructure 110, the gate mask layer 102 is used as an etch mask when thedummy gate structure 110 is formed, and the gate mask layer 102 is alsoused to protect the top of the dummy gate structure 110. Therefore, theposition, shape and number of the gate mask layer 102 correspond to theposition, shape and number of the dummy gate structure 110.

In some implementations, the gate mask layer 102 is also used as an etchbarrier layer during the subsequent formation of a contact hole, therebydefining a stop position of the self-aligned etching process.

The material of the gate mask layer 102 includes one or more of siliconnitride, silicon carbide and silicon carbonitride. In someimplementations, the material of the gate mask layer 102 is siliconnitride. The silicon nitride material has a relatively large density andhardness, which accordingly increase the mechanical strength of the gatemask layer 102, thereby improving the etching mask function of the gatemask layer 102 and the function of defining the stop position of thesubsequent self-aligned etching process.

In some implementations, a side wall layer 101 is further formed on thesidewall of the dummy gate structure 110. The side wall layer 101 isused to define a formation region of the source/drain doping region 115,and the side wall layer 101 is further used to protect the dummy gatestructure 110 and the sidewall of the subsequently formed gate structurein subsequent processes.

The material of the side wall layer 101 may be at least one of siliconoxide, silicon nitride, silicon oxynitride, silicon carbide, siliconoxycarbonitride, silicon oxycarbide, boron nitride or boron oxycarbide.The side wall layer 101 may be a single-layer structure or a stackedstructure. In some implementations, the side wall layer 101 is asingle-layer structure, and the material of the side wall layer 101 issilicon nitride.

The source/drain doping region 115 is located in the base 100 on bothsides of the dummy gate structure 110.

When an NMOS transistor is formed, the source/drain doping region 115includes a stress layer doped with an N-type ion, the material of thestress layer is Si or SiC, and the stress layer provides a tensilestress to a channel region of the NMOS transistor, thereby facilitatingthe increase of the carrier mobility of the NMOS transistor, where theN-type ion is a P ion, an As ion or an Sb ion.

When a PMOS transistor is formed, the source/drain doping region 115includes a stress layer doped with a P-type ion, the material of thestress layer is Si or SiGe, and the stress layer provides a pressurestress to a channel region of the PMOS transistor, thereby facilitatingthe increase of the carrier mobility of the PMOS transistor, where theP-type ion is a B ion, a Ga ion or an In ion.

In some implementations, a contact etch stop layer (CESL) 105 is alsoformed on the base 100 to conformally cover the source/drain dopingregion 115, the sidewall of the side wall layer 101 and the top of thegate mask layer 102. Accordingly, the dielectric layer 116 covers thecontact etch stop layer 105.

The contact etch stop layer 105 located on the top of the source/draindoping region 115 is used to define a stop position in a subsequentcontact etch process, thereby reducing the damage of the contact etchprocess to the source/drain doping region 115. The contact etch stoplayer 105 located on the sidewall of the side wall layer 101 and theside wall layer 101 form a side wall structure, thereby protecting thesidewall of the dummy gate structure 110. The contact etch stop layer105 located on the gate mask layer 102 is used to protect the top of thedummy gate structure 110 together with the gate mask layer 102.

In some implementations, the material of the contact etch stop layer 105is silicon nitride. The silicon nitride material has a relatively largedensity and hardness, so as to ensure that the contact etch stop layer105 can achieve the functions of defining an etch stop position in asubsequent contact etch process and protecting the dummy gate structure110.

In some implementations, in the step of providing the base 100, thedielectric layer 116 covers the sidewall of the dummy gate structure110, and the dielectric layer 116 also covers the gate mask layer 102.Specifically, the dielectric layer 116 covers the contact etch stoplayer 105 located on the top of the gate mask layer 102.

The dielectric layer 116 is used to isolate adjacent devices, and thedielectric layer 116 also provides a process platform for forming acontact plug 120 and subsequently forming a gate structure.

Therefore, the material of the dielectric layer 116 is an insulatingmaterial such as one or more of silicon oxide, silicon nitride, siliconoxynitride, silicon oxycarbide, carbonitride and siliconoxycarbonitride. In some implementations, the material of the dielectriclayer 116 is silicon oxide.

Referring to FIG. 8 to FIG. 10, the dielectric layer 116 on both sidesof the dummy gate structure 110 are etched to form a contact hole 160exposing the source/drain doping region 115 (as shown in FIG. 10).

The contact hole 160 provides a spatial position for subsequentformation of a contact plug.

In some implementations, a contact hole 160 exposing the top of thesource/drain doping region 115 is formed, and the subsequent processfurther includes: forming a contact plug in the contact hole 160.Therefore, after a gate opening is formed by subsequently removing thegate mask layer 102 and the dummy gate structure 110 and forming a gatestructure in the gate opening, the steps of removing the gate structureof a partial thickness and forming a protective layer on the top of theremaining gate structure are not required additionally, therebyfacilitating simplification of the process complexity and reduction ofthe process difficulty. Moreover, the step of removing the gatestructure of a partial thickness is eliminated, so that it isunnecessary to form a dummy gate structure 110 and a gate structurehaving an excessively large height. Accordingly, it is advantageous toincrease the process windows for forming the dummy gate structure 110,removing the dummy gate structure 110 and forming the gate structure. Insummary, in some implementations it is advantageous to simplify theprocess complexity and increase the process windows.

In some implementations, a gate mask layer 102 is formed on the top ofthe dummy gate structure 110. Therefore, through a self-aligned contactetch process, the gate mask layer 102 is used as an etch barrier layerto etch the dielectric layer 116 on both sides of the dummy gatestructure 110, and a contact hole 160 exposing the top of thesource/drain doping layer 115 is formed in the dielectric layer 116,thereby further improving the process window for forming the contacthole 160.

Specifically, in some implementations, the step of forming the contacthole 160 includes the following steps:

As shown in FIG. 8, a pattern layer 119 is formed on the dielectriclayer 116, a pattern opening 140 exposing the top of the dielectriclayer 116 above the source/drain doping region 115 is formed in thepattern layer 119, and the pattern opening 140 also extending above thepartial top of the gate mask layer 102 in a direction perpendicular to asidewall of the dummy gate structure 110.

The pattern layer 119 is used as an etch mask for subsequently etchingthe dielectric layer 116 to form a contact hole.

The pattern opening 140 also extends above the partial top of the gatemask layer 102, thereby reducing the process difficulty of forming thepattern opening 140, and facilitating increase of the process window forforming the pattern opening 140.

In some implementations, the material of the pattern layer 119 is aphotoresist. The step of forming the pattern layer 119 may accordinglyinclude: forming a photoresist layer (not shown) on the dielectric layer116, and patterning the photoresist layer by using processes such asexposure and development to form the pattern layer 119.

In some implementations, before forming the pattern layer 119, themethod further includes: forming a planar layer 117 (as shown in FIG. 8)on the top of the dielectric layer 116, and forming an anti-reflectivecoating 118 (as shown in FIG. 8) on the planar layer 117. The patternlayer 119 is accordingly formed on the anti-reflective coating 118.

The planar layer 117 is used to provide a planar surface for forming thepattern layer 119, thereby improving the pattern precision of thepattern layer 119 such that the profile, size, and formation position ofthe pattern layer 119 satisfy the process requirements. In someimplementations, the material of the planar layer 117 is a spin oncarbon (SOC) material.

In other implementations, the material of the planar layer may also bean organic dielectric layer (ODL) material or a deep UV light absorbingoxide (DUO) material.

The anti-reflective coating 118 is used to reduce the reflection effectat the time of exposure, thereby improving the transfer precision of apattern. In some implementations, the anti-reflective coating 118 is asilicon-anti reflective coating (Si-ARC) layer, where the Si-ARC layeris advantageous to increase the exposure depth of field (DOF) during thephotoetching process, and advantageous to improve the uniformity ofexposure. Moreover, the Si-ARC layer is rich in silicon, so that it isalso advantageous to increase the hardness of the anti-reflectivecoating 118, thereby facilitating further improvement of the transferprecision of a pattern.

In other implementations, the anti-reflective coating may also be othersuitable anti-reflective materials, such as bottom anti-reflectivecoating (BARC) materials.

As shown in FIG. 9 and FIG. 10, the dielectric layer 116 exposed by thepattern opening 140 (as shown in FIG. 8) is etched by using the patternlayer 119 (as shown in FIG. 8) as a mask.

In some implementations, in the step of etching the dielectric layer 116exposed by the pattern opening 140, the gate mask layer 102 serves as anetch barrier layer, and can function to define an etch stop position,thereby preventing damage to the top of the dummy gate structure 110 bythe etching process.

It is also to be noted that in the step of etching the dielectric layer116 exposed by the pattern opening 140, the side wall layer 101 and thecontact etch stop layer 105 located on the sidewall of the side walllayer 101 can achieve an etch barrier function, thereby preventingdamage to the sidewall of the dummy gate structure 110 by the etchingprocess.

Specifically, the step of forming the contact hole 160 includes:etching, as shown in FIG. 9, the dielectric layer 116 on the top of thesource/drain doping region 115, using the pattern layer 119 as a mask,to form an initial contact hole 150, where the bottom of the initialcontact hole 150 exposes the contact etch stop layer 105 located on thetop of the source/drain doping region 115; and removing, as shown inFIG. 10, the contact etch stop layer 105 exposed by the bottom of theinitial contact hole 150 to form the contact hole 160 penetrating thedielectric layer 116 and the contact etch stop layer 105.

In some implementations, a planar layer 117 and an anti-reflectivecoating 118 are further formed on the dielectric layer 116. Therefore,before the dielectric layer 116 on the top of the source/drain dopingregion 115 is etched, the anti-reflective coating 118 and the planarlayer 117 are etched using the pattern layer 119 as a mask.

In some implementations, the dielectric layer 116 on both sides of thedummy gate structure 110 is etched by a dry etching process. The dryetching process is easy to achieve anisotropic etching, and the profilecontrol is better, which is advantageous for the profile of the initialcontact hole 150 to satisfy the process requirements.

It is to be noted that, in some implementations, in the step of etchingthe dielectric layer 116, the pattern layer 119 and the anti-reflectivecoating 118 also generate losses. Therefore, only the planar layer 117remains on the top of the dielectric layer 116 after the initial contacthole 150 is formed.

In some implementations, the contact etch stop layer 105 exposed by thebottom of the initial contact hole 150 is removed by a dry etchingprocess. The dry etching process is easy to achieve anisotropic etching,to reduce the loss of the contact etch stop layer 105 on the sidewall ofthe side wall layer 101.

In other implementations, the contact etch stop layer exposed by thebottom of the initial contact hole may also be removed by a wet etchingprocess according to actual processes.

It is also to be noted that, in some implementations, after removing thecontact etch stop layer 105 exposed by the bottom of the initial contacthole 150, the method further includes: removing the planar layer 117.Specifically, the planar layer 117 may be removed by an ashing process.

It is to be noted that, some implementations are exemplified by thecontact hole 160 being formed by a self-aligned contact etching process.In other implementations, the contact hole may also be formed by anon-SAC etching process according to process requirements. That is, thepattern opening is located in the dielectric layer on both sides of thedummy gate structure.

Referring to FIG. 11 and FIG. 12, a contact plug 120 (shown in FIG. 12)is formed in the contact hole 160 (shown in FIG. 10), where the contactplug 120 is electrically connected to the source/drain doping region115.

The contact plug 120 is used to achieve an electrical connection betweenthe source/drain doping region 115 and an external circuit or otherinterconnect structures.

In some implementations, the material of the contact plug 120 is W. Inother implementations, the material of the contact plug may also be Al,Cu or TiAl.

In some implementations, in the step of providing the base 100, thedielectric layer 116 covers the top of the dummy gate structure 110.Specifically, the dielectric layer 116 covers the gate mask layer 102 onthe top of the dummy gate structure 110.

In some implementations, the step of forming the contact plug 120includes the following steps:

As shown in FIG. 11, a conductive layer 106 filled in the contact hole160 is formed, where the conductive layer 106 also covers the top of thedielectric layer 116.

The conductive layer 106 is used to form the contact plug 120.

In some implementations, the conductive layer 106 is formed by achemical vapor deposition process.

As shown in FIG. 12, the conductive layer 106 above the top of thedielectric layer 116 is removed by a planarization process. After theplanarization process, the remaining conductive layer 106 of a partialthickness is etched back, and the remaining conductive layer 106 in thecontact hole 160 is retained as the contact plug 120.

The conductive layer 106 above the top of the dielectric layer 116 isremoved by a planarization process to improve the flatness and heightuniformity of the top surface of the remaining conductive layer 106after the planarization process, and further improve the top flatnessand height uniformity of the contact plug 120.

Specifically, the planarization process may be performed by using achemical mechanical grinding process.

In some implementations, the remaining conductive layer 106 of a partialthickness is etched back by using a dry etching process. The dry etchingprocess is used to accurately control the etching amount of theconductive layer 106, so that the height of the contact plug 120satisfies the process requirements, and the dry etching process isadvantageous to improve the etching efficiency.

In some implementations, in the step of forming the contact plug 120,the top of the contact plug 120 is lower than the top of the dummy gatestructure 110, so as to provide a process basis for subsequently forminga protective layer on the top of the contact plug 120.

Therefore, after the contact plug 120 is formed, the adjacent dummy gatestructure 110 and the contact plug 120 define a groove 180 (as shown inFIG. 12).

Accordingly, with reference to FIG. 13 and FIG. 14, the formation methodfurther includes: forming a protective layer 122 (as shown in FIG. 12)on the top of the contact plug 120.

The protective layer 122 is used to protect the top of the contact plug120, so as to prevent loss of the contact plug 120 in the subsequentsteps of removing the dummy gate structure 110 to form a gate openingand forming a gate structure in the gate opening, thereby beingadvantageous to prevent the contact plug 120 from bridging with thesubsequent gate structure.

Specifically, the protective layer 122 is formed in the groove 180.

In some implementations, the material of the protective layer 122 issilicon oxide. Specifically, the material of the protective layer 122may include tetraethoxysilane (TEOS) or flowable chemical vapordeposition (FCVD) silicon oxide.

Silicon oxide is a commonly used material in a semiconductor process,which is advantageous to improve process compatibility and achieve lowprocess cost. The subsequent process generally further includes the stepof etching the protective layer 122 to expose the contact plug 120. Theetching process is easily performed by selecting silicon oxide.

It is to be noted that the thickness of the protective layer 122 shouldnot be too small or too large. If the thickness of the protective layer122 is too small, the protective layer 122 is easily consumedprematurely, thereby easily reducing the protective effect of theprotective layer 122 on the contact plug 120. If the thickness of theprotective layer 122 is too large, the method further subsequentlyincludes the step of etching the protective layer 122 to expose thecontact plug 120. The process of etching the protective layer 122 isdifficult accordingly. Moreover, the thickness of the protective layer122 is too large, and the height of the contact plug 120 will be toosmall accordingly, thereby easily affecting the performance of thecontact plug 120. To this end, in the step of forming the protectivelayer 122 in some implementations, the protective layer 122 has athickness of 150 A to 500 A.

In some implementations, in the step of forming the protective layer122, the top of the protective layer 122 is flush with the top of thedummy gate structure 110, thereby providing a planar surface forsubsequent processes, and further improving the process stability ofsubsequent processes.

In some implementations, the step of forming the protective layer 122includes the following steps:

As shown in FIG. 13, a protective material layer 121 is formed andfilled in the remaining contact hole 180 exposed by the contact plug120.

The protective material layer 121 is used to form the protective layer122.

In some implementations, the protective material layer 121 is formed bya spin process. The top surface flatness of the protective materiallayer 121 is improved by a spin process. Moreover, due to the spinprocess, the step of removing the protective material layer above thetop of the dielectric layer is not required, which is advantageous tosimplify the process steps.

In other implementations, the protective material layer may also beformed by using a flowable chemical vapor deposition process.

As shown in FIG. 14, the protective material layer 121 above the top ofthe dummy gate structure 110 is removed by using a planarizationprocess, and the protective material layer 121 remains as the protectivelayer 122.

Specifically, the planarization process is a chemical mechanicalgrinding process or a dry etching process.

In some implementations, the planarization process is performed by achemical mechanical grinding process, and the protective material layer121 is easily ground by using the top of the dummy gate structure 110 asa stop position.

In some implementations, in the step of the planarization process, thedielectric layer 116 above the top of the dummy gate structure 110 isremoved, and the top of the dummy gate structure 110 is exposed to makepreparations for subsequently removing the dummy gate structure 110.

In the step of the planarization process, the gate mask layer 102, thedielectric layer 116, the contact etch stop layer 106 and the side walllayer 101 above the top of the dummy gate structure 110 are alsoremoved.

Referring to FIG. 15, after the contact plug 120 is formed, the dummygate structure 110 (as shown in FIG. 14) is removed, and a gate opening170 is formed in the dielectric layer 116.

The gate opening 170 provides a spatial position for subsequentformation of a gate structure.

In some implementations, in the step of forming the protective layer122, the gate mask layer 102 is removed, and the top of the dummy gatestructure 110 is exposed.

Therefore, the step of forming the gate opening 170 includes: removingthe dummy gate structure 110 after forming the protective layer 122.

In some implementations, the dummy gate structure 110 is removed by adry etching process, which is advantageous to improve the etchingefficiency and the profile quality of the gate opening 170.

Referring to FIG. 16 and FIG. 17, a gate structure 130 (as shown in FIG.17) is formed in the gate opening 170 (as shown in FIG. 15).

It can be seen from the foregoing that some implementations does notneed to additionally perform the step of removing the gate structure ofa partial thickness and the step of forming the protective layer on thetop of the remaining gate structure, so it is unnecessary to form a gatestructure having an excessively large height, which is advantageous toincrease the process window for forming the gate structure 130.

The gate structure 130 is used to control the opening or closing of aconductive channel when the device is in operation.

In some implementations, the gate structure 130 is a metal gatestructure. The gate structure 130 correspondingly includes a gatedielectric layer (not shown) on the bottom and sidewall of the gateopening 170, a work function layer (not shown) conformally covering thegate dielectric layer, and a gate electrode layer (not shown) located inthe remaining gate opening 170 exposing the work function layer.

In some implementations, the gate dielectric layer includes a high-kdielectric layer, and the material of the gate dielectric layer is ahigh-k dielectric material, where the high-k dielectric material refersto a dielectric material having a relative dielectric constant greaterthan a relative dielectric constant of silicon oxide. Specifically, thematerial of the gate dielectric layer is HfO₂. In other implementations,the material of the gate dielectric layer may also be selected fromZrO₂, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al₂O₃.

In still other implementations, the gate dielectric layer may furtherinclude a gate oxide layer located on the bottom of the gate opening,and a high-k dielectric layer located on the top of the gate oxide layerand on the bottom and sidewall of the gate opening.

When an NMOS transistor is formed, the material of the work functionlayer includes one or more of titanium aluminide, tantalum carbide,aluminum, or titanium carbide. When a PMOS transistor is formed, thematerial of the work function layer includes one or more of titaniumnitride, tantalum nitride, titanium carbide, silicon tantalum nitride,silicon titanium nitride, and tantalum carbide.

In some implementations, the material of the gate electrode layer istungsten. In other implementations, the material of the gate electrodelayer may also be a magnesium-tungsten alloy, Al, Cu, Ag, Au, Pt, Ni orTi.

In some implementations, the step of forming the gate structure 130includes the following steps:

As shown in FIG. 16, an initial gate structure 123 is formed and filledin the gate opening 170, the initial gate structure 123 also coveringthe dielectric layer 116 and the protective layer 122. As shown in FIG.17, the initial gate structure 123 above the top of the protective layer122 is removed by a planarization process, the remaining initial gatestructure 123 located in the gate opening 170 serving as the gatestructure 130.

In some implementations, the step of forming the initial gate structure123 includes: forming an initial gate dielectric layer (not shown) toconformally cover the bottom and sidewall of the gate opening 170, thedielectric layer 116 and the top of the protective layer 122; andforming an initial work function layer (not shown) conformally coveringthe initial gate dielectric layer to form an initial gate electrodelayer (not shown), where the initial gate electrode layer is filled inthe remaining gate opening 170 exposed by the initial work functionlayer and covers the initial work function layer.

In some implementations, the process of forming the initial gatedielectric layer and an initial work function layer may be an atomiclayer deposition process, which is advantageous to improve the conformalcoverage capacity and thickness uniformity of the initial gatedielectric layer and the initial work function layer.

In some implementations, the process of forming the initial gateelectrode layer may be a chemical vapor deposition process.

In some implementations, the planarization process of removing theinitial gate structure 123 above the top of the protective layer 122 isa chemical mechanical grinding process.

Accordingly, the present disclosure also provides a semiconductorstructure. Referring to FIG. 14, a schematic structural diagram of anembodiment of a semiconductor structure according to the presentdisclosure is shown.

The semiconductor structure includes: a base 100; a dummy gate structure110, located on the base 100; a source/drain doping region 115, locatedin the base 100 on both sides of the dummy gate structure 110; adielectric layer 116, located on the base 100 exposed by the dummy gatestructure 110, the dielectric layer 116 exposing the top of the dummygate structure 110; and a contact plug 120, located in the dielectriclayer 116 on the top of the source/drain doping region 115, the contactplug 120 being electrically connected to the source/drain doping region115.

In some implementations, the contact plug 120 is formed first, after agate opening is formed by removing the dummy gate structure 110subsequently and a gate structure is formed in the gate opening, thesteps of removing the gate structure of a partial thickness and forminga protective layer on the top of the remaining gate structure are notrequired additionally, thereby facilitating simplification of theprocess complexity and reduction of the process difficulty. Moreover,the step of removing the gate structure of a partial thickness iseliminated, so that it is unnecessary to form a dummy gate structure 110and a gate structure having an excessively large height. Accordingly, itis advantageous to increase the process windows for forming the dummygate structure 110, removing the dummy gate structure 110 andsubsequently forming the gate structure. In summary, in someimplementations of the present disclosure, it is advantageous tosimplify the process complexity and increase the process windows.

The base 100 is used to provide a process platform for processes.

In some implementations, the base 100 is used to form a planar fieldeffect transistor, and the base 100 accordingly includes only asubstrate (not marked). In other implementations, when the base is usedto form a fin field effect transistor, the base accordingly includes asubstrate and a fin that protrudes from the substrate.

In some implementations, the substrate is a silicon substrate. In otherimplementations, the material of the substrate may also be othermaterials such as germanium, silicon germanide, silicon carbide, galliumarsenide or indium gallide, and the substrate can also be other types ofsubstrates such as a silicon substrate on an insulator or a germaniumsubstrate on an insulator. The material of the substrate may be amaterial suitable for process requirements or easy to integrate.

The dummy gate structure 110 occupies a spatial position for subsequentformation of a gate structure.

In some implementations, the dummy gate structure 110 is a single-layerstructure, the dummy gate structure 110 includes only a dummy gate layer(not marked), and the material of the dummy gate layer is polysilicon.

In other implementations, the dummy gate structure may be a stackedstructure, where the dummy gate structure accordingly includes a dummygate oxide layer and a dummy gate layer located on the dummy gate oxidelayer, and the material of the dummy gate oxide layer may be siliconoxide or silicon oxynitride.

In some implementations, the semiconductor structure further includes: aside wall layer 101, located on a sidewall of the dummy gate structure110. The side wall layer 101 is used to define a formation region of thesource/drain doping region 115, and the side wall layer 101 is furtherused to protect the dummy gate structure 110 and the sidewall of thesubsequently formed gate structure.

The material of the side wall layer 101 may be at least one of siliconoxide, silicon nitride, silicon oxynitride, silicon carbide, siliconoxycarbonitride, silicon oxycarbide, boron nitride or boron oxycarbide.The side wall layer 101 may be a single-layer structure or a stackedstructure. In some implementations, the side wall layer 101 is asingle-layer structure, and the material of the side wall layer 101 issilicon nitride.

The source/drain doping region 115 is located in the base 100 on bothsides of the dummy gate structure 110.

When an NMOS transistor is formed, the source/drain doping region 115includes a stress layer doped with an N-type ion, the material of thestress layer is Si or SiC, and the stress layer provides a tensilestress to a channel region of the NMOS transistor, thereby facilitatingthe increase of the carrier mobility of the NMOS transistor, where theN-type ion is a P ion, an As ion or an Sb ion.

When a PMOS transistor is formed, the source/drain doping region 115includes a stress layer doped with a P-type ion, the material of thestress layer is Si or SiGe, and the stress layer provides a pressurestress to a channel region of the PMOS transistor, thereby facilitatingthe increase of the carrier mobility of the PMOS transistor, where theP-type ion is a B ion, a Ga ion or an In ion.

In some implementations, the semiconductor structure further includes: acontact etch stop layer 105, located on a sidewall of the side walllayer 101. The contact etch stop layer 105 is used to protect the topand sidewall of the dummy gate structure 110 as well as the source/draindoping region 115 in the step of forming the contact plug 120.

In some implementations, the material of the contact etch stop layer 105is silicon nitride. The silicon nitride material has a relatively largedensity and hardness, so as to ensure that the contact etch stop layer105 can achieve the functions of protecting the dummy gate structure 110and the source/drain doping region 115.

In some implementations, the dielectric layer 116 covers the sidewall ofthe dummy gate structure 110.

The dielectric layer 116 is used to isolate adjacent devices, and thedielectric layer 116 also provides a process platform for forming acontact plug 120 and subsequently forming a gate structure.

Therefore, the material of the dielectric layer 116 is an insulatingmaterial such as one or more of silicon oxide, silicon nitride, siliconoxynitride, silicon oxycarbide, carbonitride and siliconoxycarbonitride. In some implementations, the material of the dielectriclayer 116 is silicon oxide.

The contact plug 120 is used to achieve an electrical connection betweenthe source/drain doping region 115 and an external circuit or otherinterconnect structures.

In some implementations, the material of the contact plug 120 is W. Inother implementations, the material of the contact plug may also be Al,Cu or TiAl.

In some implementations, the top of the contact plug 120 is lower thanthe top of the dummy gate structure 110, so as to provide a processbasis for forming a protective layer 122. Accordingly, the adjacentdummy gate structure 110 and the contact plug 120 define a groove 180(as shown in FIG. 12).

In some implementations, the semiconductor structure further includes: aprotective layer 122, located on the top of the contact plug 120.

The protective layer 122 is used to protect the top of the contact plug120, so as to prevent loss of the contact plug 120 in the subsequentsteps of removing the dummy gate structure 110 to form a gate openingand forming a gate structure in the gate opening, thereby beingadvantageous to prevent the contact plug 120 from bridging with thesubsequent gate structure.

In some implementations, the protective layer 122 is located in thegroove 180 (as shown in FIG. 12).

In some implementations, the material of the protective layer 122 issilicon oxide. Specifically, the material of the protective layer 122may include tetraethoxysilane (TEOS) or flowable chemical vapordeposition (FCVD) silicon oxide.

Silicon oxide is a commonly used material in a semiconductor process,which is advantageous to improve process compatibility and achieve lowprocess cost. The subsequent process generally further includes the stepof etching the protective layer 122 to expose the contact plug 120. Theetching process is easily performed by selecting silicon oxide.

It is to be noted that the thickness of the protective layer 122 shouldnot be too small or too large. If the thickness of the protective layer122 is too small, the protective layer 122 is easily consumedprematurely, thereby easily reducing the protective effect of theprotective layer 122 on the contact plug 120. If the thickness of theprotective layer 122 is too large, the method further subsequentlyincludes the step of etching the protective layer 122 to expose thecontact plug 120. The process of etching the protective layer 122 isdifficult accordingly. Moreover, the thickness of the protective layer122 is too large, and the height of the contact plug 120 will be toosmall accordingly, thereby easily affecting the performance of thecontact plug 120. To this end, in the step of forming the protectivelayer 122 in some implementations, the protective layer 122 has athickness of 150 A to 500 A.

Specifically, the top of the protective layer 122 is flush with the topof the dummy gate structure 110, thereby providing a planar surface forsubsequent processes, and further improving the process stability ofsubsequent processes.

The semiconductor structure may be formed by the formation methodaccording to the foregoing embodiment, or may also be formed by otherformation methods. For a detailed description of the semiconductorstructure in some implementations, reference may be made to thecorresponding description in the foregoing embodiments, and thedescriptions are omitted here in some implementations.

Although the present disclosure is disclosed above, the presentdisclosure is not limited thereto. A person skilled in the art can makevarious changes and modifications without departing from the spirit andscope of the present disclosure, and the scope of the present disclosureshould be determined by the scope defined by the claims.

What is claimed is:
 1. A semiconductor structure, comprising: a base; adummy gate structure, located on the base; a source/drain doping region,located in the base on both sides of the dummy gate structure; adielectric layer, located on the base exposed by the dummy gatestructure, the dielectric layer exposing a top of the dummy gatestructure; and a contact plug, located in the dielectric layer on a topof the source/drain doping region, the contact plug being electricallyconnected to the source/drain doping region.
 2. The semiconductorstructure according to claim 1, wherein: a top of the contact plug islower than the top of the dummy gate structure; and the semiconductorstructure further comprises: a protective layer, located on the top ofthe contact plug.
 3. The semiconductor structure according to claim 2,wherein: the top of the contact plug is lower than the top of the dummygate structure; and a top of the protective layer is flush with the topof the dummy gate structure.
 4. The semiconductor structure according toclaim 2, wherein the material of the protective layer comprises siliconoxide.
 5. The semiconductor structure according to claim 2, wherein theprotective layer has a thickness of 150 Å to 500 Å.